QUOTE(Brian Davis @ Oct 4 2007, 09:42 PM)

On the plus side, there are folks like Ralph Hempel who have cycled the lock bits many hundreds (thousands?) of times in the process of developing FW without killing them. Presumably they *will* wear out, but I don't think anybody has managed to do it yet.
The CPU has both a security bit and 16 lock bits.
The intent behind the security bit is to prevent reverse engineering the firmware in a microprocessor. It works as follows:
- With bit set, flash memory can only be accessed during execution of firmware. You can't connect a hardware debugger to read the contents of flash memory do that you can subsequently reverse engineer the code.
- When you clear security bit, it also forces a complete erase of flash memory.
The intent behind lock bit is to prevent inadvertent erase of a block of flash memory. Each lock bit covers 16K of flash. You cannot write or erase within a 16K block if the corresponding lock bit is set.
As far as I can tell, the security bit and lock bits are not set within the NXT firmware. I know after firmware download my JTAG debugger works fine -- thus security bit is not being set. And I don't recall seeing any code to set / clear the lock bits as part of the NXT's flash based file system.
Boot mode is controlled by an external input line on the NXT CPU. Going into boot mode does not involve writing or clearing any of the security/lock bits! In boot mode an "invisible" block of ROM is made visible to the CPU memory space and this ROM contains a minimal program containing the bootstrap loader and will accept the commands for SAMBA. SAMBA is the name given to the Boot Loader. (i.e. SAM Boot Assistant where "SAM" is an Atmel CPU acronym). The NXT CPU is a SAM7S256 chip.
I am not familiar with the SAMBA commands required to load firmware. Perhaps Ralph and/or the NXJ team can comment. If the lock or security bits are set, you'd have to issue SAMBA commands to clear. I don't know if these are used as part of the NXT firmware download process because, as described above, the bits are not set.
You'd also think that when Atmel was writing the SAMBA code they would do it to minimize unnecessary erases of the security / lock bits. Atmel would certainly understand the desire to minimize erasures of these bits. If bit was already erased, then perhaps SAMBA has code to bypass the erase operation.
As well, according to the Atmel documentation, these bits are rated for 100 write/erase cycles. I can't tell from the documentation but I suspect that if a bit is already in the erased state and an erase opcode is executed then it may not count against the 100 cycles.
So it might turn out that the whole issue of exceeding the 100 cycles of write/erase on the lock/security bits is not really an issue at all. And then the "wear out" limit becomes the 10K limit on erasing a single 256-byte sector of flash.
The 10K limit is not that large. The file system VTOC is always stored as the last sector in flash. Assume two writes to it to store a file in the flash -- one to erase the existing file with same name, and second to write the new version of a file. So 5K file writes may exceed that limit. Consider a NXT used in a school or education center; 10 files writes a day may be realistic. With these assumptions, then there are possibly many NXTs that will reach the 10K limit sometime in the next year or so!
Fortuntately I understand the 10K limit is a conservative limit and I read somewhere the most common failure mode is a reduction in the 40-year retention of flash contents and not an error in writing.
I'm not really a hardware guy. It's possible I might have got some of the details wrong.